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HM66WP18512/HM66WP36256
9M Pipelined Zero Bus Latency (ZBL) SRAM (HM66WP18512) 512-Kword x 18-bit (HM66WP36256) 256-Kword x 36-bit
ADE-203-1284D (Z) Preliminary Rev. 0.4 Jun. 21, 2002 Description
The HM66WP18512 is a synchronous fast static RAM organized as 512-Kword x 18-bit. The HM66WP36256 is a synchronous fast static RAM organized as 256-Kword x 36-bit. It has realized high speed access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 100pin LQFP. Note: All power supply (VDD, VDDQ) and ground (VSS) pins must be connected for proper operation of the device. TM TM ZBL: Zero Bus Latency and compatible ZBT SRAM. ZBT is trademark of Integrated Device Technology, Inc.,
Features
* 3.3 V or 2.5V power supply, 3.3 V or 2.5 V I/O supply voltage * Clock frequency: 250/166 MHz * Fast clock access time: 2.6/3.5 ns (max) * Low operating current: 250/200 mA (max) * Address data pipeline capability * Internal input registers (Address, Data, Control) * Internal self-timed write cycle * ADV/LD burst control pins * Internally synchronized registered outputs eliminate the need to control OE * Individual byte write control * Power down state via ZZ * Common data inputs and data outputs * High board density 100-pin LQFP package * Burst control selected pin LBO (Interleave or linear burst order)
Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest Hitachi's Sales Dept. regarding specifications.
HM66WP18512, HM66WP36256
Ordering Information
Type No. HM66WP18512FP-40 HM66WP18512FP-60 HM66WP36256FP-40 HM66WP36256FP-60 Access time 2.6 ns 3.5 ns 2.6 ns 3.5 ns CPU clock rate 250 MHz 166 MHz 250 MHz 166 MHz Package LQFP 100-pin (FP-100H)
Rev.0.4, Jun. 2002, page 2 of 22
HM66WP18512, HM66WP36256
Pin Arrangement (HM66WP36256) 100PIN-LQFP
100-pin LQFP
ADV/ NC A17 A8 A9
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
VDD VSS CLK
CE2
A6 A7
DQc0 DQc1 DQc2 V DDQ V SSQ DQc3 DQc4 DQc5 DQc6 V SSQ V DDQ DQc7 DQc8
V DD (1) V DD V DD V SS
DQd8 DQd7 V DDQ
V SSQ
DQd6 DQd5 DQd4 DQd3 V SSQ V DDQ DQd2 DQd1 DQd0
Note: Pins 14 and 66 are not VDD Supply, but have to be connected VDD.
A5 A4 A3 A2 A1 A0 NC NC V SS V DD NC NC A10 A11 A12 A13 A14 A15 A16
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
DQb0 DQb1 DQb2 V DDQ V SSQ DQb3 DQb4 DQb5 DQb6 V SSQ V DDQ DQb7 DQb8 V SS V DD (1) V DD ZZ DQa8 DQa7 V DDQ V SSQ DQa6 DQa5 DQa4 DQa3 V SSQ V DDQ DQa2 DQa1 DQa0
(Top view)
Rev.0.4, Jun. 2002, page 3 of 22
HM66WP18512, HM66WP36256
Pin Arrangement (HM66WP18512) 100PIN-LQFP
100-pin LQFP
ADV/ NC A18 A8 A9
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
VDD VSS CLK
CE2 NC NC
A6 A7
NC NC NC
VDDQ VSSQ NC NC DQb8 DQb7 VSSQ VDDQ DQb6 DQb5 VDD (1) VDD VDD VSS DQb4 DQb3 VDDQ VSSQ
DQb2 DQb1 DQb0 NC V
SSQ
VDDQ
NC NC NC
Note: Pins 14 and 66 are not VDD Supply, but have to be connected VDD.
Rev.0.4, Jun. 2002, page 4 of 22
A5 A4 A3 A2 A1 A0 NC NC V SS V DD NC NC A11 A12 A13 A14 A15 A16 A17
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A10 NC NC V DDQ V SSQ NC DQa8 DQa7 DQa6 V SSQ V DDQ DQa5 DQa4 V SS V DD (1) V DD ZZ DQa3 DQa2 V DDQ V SSQ DQa1 DQa0 NC NC V SSQ V DDQ NC NC NC
(Top view)
HM66WP18512, HM66WP36256
Pin Description (See Detailed Pin Description)
Name A0, A1 and A2-17 (HM66WP36256) A0, A1 and A2-18 (HM66WP18512) BWm I/O type Input Input Input Description 18 address inputs 19 address inputs Byte write enables BWa controls DQa0 to DQa8 BWb controls DQb0 to DQb8 BWc controls DQc0 to DQc8 BWd controls DQd0 to DQd8 Write enable Clock Chip enable Output enable Address load control Clock enable control Power down Burst mode control No connection m = a, b, c, d (HM66WP36256) m = a, b (HM66WP18512) VDD VDDQ VSS Supply Supply Supply Power supply I/O power supply Ground m = a, b, c, d (HM66WP36256) m = a, b (HM66WP18512) Notes
WE CLK CE1, CE3, CE2 OE ADV/LD CEN ZZ LBO NC DQmn n=0-8
Input Input Input Input Input Input Input Input --
Input/Output Data input/output
Rev.0.4, Jun. 2002, page 5 of 22
HM66WP18512, HM66WP36256
Detailed Pin Description
Pin number(s) Symbol LQFP 35, 34, 33, 32, 44, 45, 46, 47, 48, 49, 50, 81, 82, 83, 99, 100 37, 36 80 93, 94, 95, 96 A (x 36-bit x 18-bit common) A0, A1 A (x 18-bit) BWa, BWb BWc, BWd (x 36-bit) Input Synchronous byte write enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. BWa controls DQa0 to DQa8. BWb controls DQb0 to DQb8. BWc controls DQc0 to DQc8. BWd controls DQd0 to DQd8. Data I/O are tristated if any of these four inputs are LOW. Input Synchronous address inputs: These inputs are registered and must meet setup and hold times around the rising edge of CLK. Burst address inputs Type Description
93, 94 87 88
BWa, BWb (x 18-bit) CEN WE Input Synchronous clock enable: This active LOW internal clock signal is active. Input Synchronous write enable: This active LOW input permits write operations and must meet the setup and hold times around the rising edge of CLK. Input Clock: This signal latches the address, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Input Synchronous chip enable: This active LOW input is used to enable the device. This input is sampled only when an external address is loaded. This input can be used for memory depth expansion. Input Input Synchronous chip enable: This active HIGH input is used to enable the device. This input sampled only when a new external address is load. This input can be used for memory depth expansion. Input Output enable: This active LOW asynchronous input enables the data I/O output drivers. Input Synchronous address advance or load control: This active HIGH input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A LOW input is caused a new external address to be latched.
89
CLK
98
CE1
92 97
CE3 CE2
86 85
OE ADV/LD
Rev.0.4, Jun. 2002, page 6 of 22
HM66WP18512, HM66WP36256
Detailed Pin Description (cont)
Pin number(s) LQFP 38, 39, 42, 43, 84, NC (x 36-bit) No Connect: These signals are internally not connected. No Connect: These signals are internally not connected. Symbol Type Description
1, 2, 3, 6, 7, 25, 28, 29, NC 30, 38, 39, 42, 43, 51, (x 18-bit) 52, 53, 56, 57, 75, 78, 79, 84, 95, 96 51, 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, 80, 1, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29, 30 DQmn Input/ m = a, b, Output c, d n=0-8 (x 36-bit)
SRAM data I/O: Byte a is DQa0 to DQa8; Byte b is DQb0 to DQb8; Byte c is DQc0 to DQc8; Byte d is DQd0 to DQd8. Input data must meet setup and hold times around the rising edge of CLK.
58, 59, 62, 63, 68, 69, DQmn Input/ 72, 73, 74, 8, 9, 12, 13, m = a, b Output 18, 19, 22, 23, 24 n=0-8 (x 18-bit) 14, 15, 16, 41, 65, 66, 91 4, 11, 20, 27, 54 61, 70, 77 VDD VDDQ Supply Supply
SRAM data I/O: Byte a is DQa0 to DQa8; Byte b is DQb0 to DQb8. Input data must meet setup and hold times around the rising edge of CLK.
Power supply: 3.3 V (+5%/-5%) or 2.5 V (+5%/-5%) I/O power supply: 3.3 V (+5%/-5%) or 2.5 V (+5%/-5%) Ground: GND Asynchronous power-down (Snooze): This active HIGH input enables SRAM to enter a power-down (Snooze) state with data retention. During Snooze state, data retention is guaranteed. At this time, internal state of the SRAM is not preserved. After Snooze state, SRAM must be initiated with CEN or ADV/LD using a new external address. This pin must be connected to VSS in systems that do not use ZZ feature. Burst order (Interleave burst or linear burst) select pin (DC) This pin must connect VDD or VDDQ or VSS.
17, 40, 67, 90, 5, 10, 21, VSS 26, 55, 60, 71, 76 64 ZZ
Supply Input
31
LBO
Input
Rev.0.4, Jun. 2002, page 7 of 22
HM66WP18512, HM66WP36256
Block Diagram (HM66WP36256)
18
CLK
CLR
Binary counter
A0
A0'
2nd address registers
3rd address registers 18
A1
A1'
A0 to A17 ADV/
18
1st address registers Write enable register 1 st byte a write register 1 st byte b write register 1 st byte c write register 1 st byte d write register Enable register
18
16
18
MUX
2 nd byte a write register 2 nd byte b write register 2 nd byte c write register 2 nd byte d write register
3 rd byte a write register 3 rd byte b write register 3 rd byte c write register 3 rd byte d write register
Byte a write driver
9
Byte b write driver
9
256k x 9 x 4 Memory array
Byte c write driver
9
Byte d write driver
9
CE2
36
36
Output registers
Input registers
36
Note: The functional block diagram illustrates simplified device operation. See truth table, detailed pin descriptions and timing diagrams for detailed information.
DQa0 to DQa8 DQb0 to DQb8 DQc0 to DQc8 DQd0 to DQd8
Rev.0.4, Jun. 2002, page 8 of 22
HM66WP18512, HM66WP36256
Block Diagram (HM66WP18512)
19 2nd address registers 3rd address registers
CLK
CLR
Binary counter
A0
A0'
A1
A1'
A0 to A18
19
1 st Address registers
19
17
19
19
ADV/ Write enable register
MUX
1 st byte a write register 1 st byte b write register Enable register
2 nd byte a write register 2 nd byte b write register
3 rd byte a write register 3 rd byte b write register
Byte a write driver
9 512k x 9 x 2 Memory array 9
Byte b write driver
CE2
18 18
Output registers
Input registers
18
DQa0 to DQa8 Note: The functional block diagram illustrates simplified device operation. DQb0 to DQb8 See truth table, detailed pin descriptions and timing diagrams for detailed information.
Rev.0.4, Jun. 2002, page 9 of 22
HM66WP18512, HM66WP36256
Synchronous Truth Table
Operation Deselected cycle, power-down Deselected cycle, power-down Deselected cycle, power-down WRITE cycle, begin burst NOP/WRITE Abort, begin burst READ cycle, begin burst Dummy READ cycle, begin burst WRITE cycle, continue burst WRITE Abort, continue burst READ cycle, continue burst Address None None None External External External External Next Next Next ADV/ CE1 CE3 CE2 LD CEN WE H x x L L L L x x x x x x x x H x L L L L x x x x x x x x x L H H H H x x x x x x x L L L L L L L H H H H x x x L L L L L L L L L L L H H H x x x L L H H x x x x x x x BWm OE CLK DQ x x x L H x x L H x x x x x x x x x x L x x L x L-H High-Z L-H High-Z L-H High-Z L-H D L-H High-Z L-H Q
H L-H High-Z L-H D L-H High-Z L-H Q
Dummy READ cycle, continue burst Next WRITE cycle, suspend READ cycle, suspend Dummy READ cycle, suspend Current Current Current
H L-H High-Z L-H -
L L-H Q H L-H High-Z
Notes: 1. H means logic HIGH, L means logic LOW. x means H or L. BWm = L means any one or more byte write enable signals (BWa, BWb, BWc or BWd) are LOW. BWm = H means all byte write enable signals are HIGH. 2. BWa enables write to Bytea (DQa0 to DQa8). BWb enables write to Byteb (DQb0 to DQb8). BWc enables write to Bytec (DQc0 to DQc8). BWd enables write to Byted (DQd0 to DQd8). 3. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 4. A WRITE is performed by setting one or more byte write enable signals and WE LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification. 5. The status for DQ described in this synchronous truth table appears two clocks after the cycle in which the Read or Write command is asserted. 6. If ADV/LD is sampled High that it is continue burst cycle follows before the operation cycle. 7. Wait states are inserted by CEN = High. When CEN is sampled High after Read cycle, the Read data is maintain as output data. When CEN is sampled High after Write cycle, the Write Input Data is ignored and is maintained High-Z. Refer to Timing diagram for clarification.
Rev.0.4, Jun. 2002, page 10 of 22
HM66WP18512, HM66WP36256
Asynchronous Truth Table
Operation Read Read Write Deselect Power down (Snooze) ZZ L L L L H OE L H x x x I/O status Data out High-Z High-Z, Data in High-Z High-Z
Note: H means logic HIGH. L means logic LOW. x means H or L.
Partial Truth Table for Writes
Operation Read No write Write byte a Write all bytes WE H L L L BWa x H L L BWb x H H L BWc x H H L BWd x H H L
Note: H means logic HIGH. L means logic LOW. x means H or L.
Interleave Sequence Table (LBO = VDD or VDDQ)
Parameter External address 1st internal address 2nd internal address 3rd internal address Sequence 1 (A1, A0) 00 01 10 11 Sequence 2 (A1, A0) 01 00 11 10 Sequence 3 (A1, A0) 10 11 00 01 Sequence 4 (A1, A0) 11 10 01 00
Note: Each sequence wraps around to its initial state upon completion.
Linear Sequence Table (LBO = VSS)
Parameter External address 1st internal address 2nd internal address 3rd internal address Sequence 1 (A1, A0) 00 01 10 11 Sequence 2 (A1, A0) 01 10 11 00 Sequence 3 (A1, A0) 10 11 00 01 Sequence 4 (A1, A0) 11 00 01 10
Note: Each sequence wraps around to its initial state upon completion.
Rev.0.4, Jun. 2002, page 11 of 22
HM66WP18512, HM66WP36256
Absolute Maximum Ratings
Parameter Supply voltage Voltage on any pins relative to VSS Except VDD Power dissipation Operating temperature Storage temperature range (with bias) Storage temperature range (DQ) (Others) Symbol VDD VT VT PT Topr Tstg (bias) Tstg Value -0.5 to +4.6 -0.5 to VDDQ + 0.5 -0.5 to VDD + 0.5 1.6 0 to +70 -10 to +85 -55 to +125 Unit V V V W C C C
Recommended DC Operating Conditions (3.3V Power supply)
(Ta = 0 to +70C)
Parameter Supply voltage (Operating voltage range) Supply I/O voltage (3.3 V I/O) Supply I/O voltage (2.5 V I/O) Supply voltage to VSS Input high voltage (3.3 V I/O) (DQ) (Others) Input high voltage (2.5 V I/O) (DQ) (Others) Input low voltage (3.3 V I/O) Input low voltage (2.5 V I/O) Note: Symbol VDD VDDQ VDDQ VSS VIH VIH VIH VIH VIL VIL Min 3.135 3.135 2.375 0.0 2.0 2.0 1.7 1.7 -0.3 -0.3 Typ 3.3 3.3 2.5 0.0 Max 3.465 3.465 2.625 0.0 VDDQ + 0.3 VDD + 0.3 VDDQ + 0.3 VDD + 0.3 0.8 0.7 Unit V V V V V V V V V V 1 1 Note
1. -2.0 V for undershoot pulse width 20% tCYC.
Recommended DC Operating Conditions (2.5V Power supply)
(Ta = 0 to +70C)
Parameter Supply voltage (Operating voltage range) Supply I/O voltage (2.5 V I/O) Supply voltage to VSS Input high voltage (2.5 V I/O) (DQ) (Others) Input low voltage (2.5 V I/O) Note: Symbol VDD VDDQ VSS VIH VIH VIL Min 2.375 2.375 0.0 1.7 1.7 -0.3 Typ 2.5 2.5 0.0 Max 2.625 2.625 0.0 VDDQ + 0.3 VDD + 0.3 0.7 Unit V V V V V V 1 Note
1. -2.0 V for undershoot pulse width 20% tCYC.
Rev.0.4, Jun. 2002, page 12 of 22
HM66WP18512, HM66WP36256
DC Characteristics
(Ta = 0 to +70C, VDD = 3.3 V +5%/-5% or 2.5 V +5%/-5%)
HM66WP18512/HM66WP36256 -40 Parameter Input leakage current Output leakage current Operating current Symbol Min ILI ILO IDD -2 -5 Max 2 5 250 -60 Min -2 -5 Max 2 5 200 Unit A A mA Test conditions All inputs Vin = VSS to VDD OE = VIH, Vout = VSS to VDDQ Device selected, Iout = 0 mA, all inputs = VIH or VIL, cycle time = tCYC min. Device deselected all inputs = fixed and all inputs VDD - 0.2 V or 0.2 V, cycle time = tCYC min. Device deselected all inputs = fixed and all inputs VDD - 0.2 V or 0.2 V, Frequency = 0 MHz. Device deselected all inputs = fixed and all inputs VDD - 0.2 V or 0.2 V, ZZ VDD - 0.2 V, Frequency = 0 MHz. IOL = 8 mA IOH = -4 mA IOL = 1 mA IOH = -1 mA
Standby current
ISB
100
80
mA
ISB1
30
30
mA
ISBZZ
10
10
mA
Output low voltage (3.3 V I/O) Output high voltage (3.3 V I/O) Output low voltage (2.5 V I/O) Output high voltage (2.5 V I/O) Note:
VOL VOH VOL VOH
2.4 2.0
0.4 0.4
2.4 2.0
0.4 0.4
V V V V
1. LBO pin has an internal pull-up, ZZ pin has an internal pull-down, and input leakage current < |5A|.
Rev.0.4, Jun. 2002, page 13 of 22
HM66WP18512, HM66WP36256
Capacitance
(Ta = +25C, f = 1.0 MHz, VDD = 3.3 V and 2.5 V)
Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Min Typ 4 6 Max 5 7 Unit pF pF Note 1 1
1. This parameter is sampled and not 100% tested.
Rev.0.4, Jun. 2002, page 14 of 22
HM66WP18512, HM66WP36256
AC Characteristics
(Ta = 0 to +70C, VDD = 3.3 V +5%/-5% and 2.5 V +5%/-5%, VSS = 0 V) Test Conditions * * * * * Input timing measurement reference level :1.4 V (3.3 V I/O) :1.2 V (2.5 V I/O) Input pulse levels : 0 V to 2.8 V (3.3 V I/O) : 0 V to 2.4 V (2.5 V I/O) Input rise and fall time: 2 V/ns (10% - 90%) Output timing reference level : 1.4 V (3.3 V I/O) : 1.2 V (2.5 V I/O) Output load: See figure
16.7 16.7 DQ 16.7 50 5 pF* 50 5 pF* 50 VL 50 VL
VL VL = 1.4 V (3.3 V I/O) or 1.2 V (2.5 V I/O) *(Including scope and jig)
Rev.0.4, Jun. 2002, page 15 of 22
HM66WP18512, HM66WP36256
HM66WP18512/HM66WP36256 Symbol Parameter Cycle time Clock access time Output enable to output valid Clock high to output active Clock high to output change Output enable to output active Output disable to Q High-Z Clock high to Q High-Z Clock high pulse width Clock low pulse width Setup Times: Address Clock Enable Input Data Write (WE, BWa-d) Address Advance Chip Enable Hold Times: Address Clock Enable Input Data Write (WE, BWa-d) Address Advance Chip Enable ZZ Active to input ignored ZZ Inactive to input Sampled ZZ Active to sleep current ZZ Inactive to exit sleep current Standard tKHKH tKHQV tGLQV tKHQX2 tKHQX tGLQX tGHQZ tKHQZ tKHKL tKLKH tAVKH tCENVKH tDVKH tWVKH tADVVK tEVKH tKHAX tKHCENX tKHDX tKHWX tKHADVX tKHEX Alternate tCYC tCA tOE tCLZ tCOH tOLZ tOHZ tCHZ tCH tCL tSA tSCEN tSD tSW tSADV tSCE 0.3 tHA tHCEN tHD tHW tHADV tHCE tPDS tPUS tZZI tRZZI 2 2 0 2 2 2 0 2 cycle 4 cycle 4 cycle 4 cycle 4 0.5 ns -40 Min 4.0 0.8 0.8 0 1.7 1.7 1.2 Max 2.6 2.6 2.6 2.6 -60 Min 6.0 1.5 1.5 0 2.2 2.2 1.5 3.5 3.5 Max 3.5 3.5 Unit ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 Notes
Notes: 1. Transition is measured 100 mV from steady-state voltage. This parameter is sampled. 2. A READ cycle is defined by WE HIGH for the required setup and hold times. A WRITE cycle is defined by WE LOW for the required setup and hold times. 3. This is a synchronous device. All address must meet the specified setup and hold times for all rising edges of CLK when chip enabled. All other Synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when chip is enabled. Chip enable must be valid at each rising edge of CLK to remain enabled. 4. Data-output is not guaranteed during the cycle when transition of ZZ from low to high occurs.
Rev.0.4, Jun. 2002, page 16 of 22
; ;; ;
HM66WP18512, HM66WP36256
Timing Waveforms
Read Cycle
tCYC CLK tCH tCL ADV/ tSA t HA A1 Address A2 A3 t SW t HW t SCE t HCE
Deselect cycle *3 *2
; ;; ;; ;; ; ;;;; ;;;; ;; ;
t OE tOHZ t OLZ tCLZ t COH t CHZ *3 Q
Q (A1) Q (A2)*1
Q (A2+1) Q (A2+2) Q (A2+3)
Q (A2)
Q (A2+1)
Q (A3)
t CA
Burst wraps around to its initial state.
Single READ
BURST READ
H or L Undefined Notes: 1. Q (A2) refers to output from address A2. Q (A2 + 1) refers to output from next internal burst address following A2. 2. and CE2 have timing identical to . On this diagram, when is LOW, is LOW and CE2 is HIGH. When is HIGH, is HIGH and CE2 is LOW. 3. Outputs are disabled within one clock cycle after deselect. 4. ZZ is LOW.
Single READ
Deselect cycle
Rev.0.4, Jun. 2002, page 17 of 22
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HM66WP18512, HM66WP36256
Write Cycle
tCYC CLK tCH t CL ADV/ t SA t HA A1 Address A2 A3 A4 t SW tHW t SCE t HCE
*1 *2
;;; ;; ;;;; ;; ;;;;; ;;
tSD tHD
D (A1)
D
D (A2)
tOHZ
D (A3)
D (A3+1)
D (A3+2)
D (A3+3)
D (A3)
D (A4)
Q
Single WRITE
BURST WRITE
BURST WRITE
H or L Undefined
Notes: 1.
and CE2 have timing identical to . On this diagram, when is LOW, is LOW and CE2 is HIGH. When is HIGH, is HIGH and CE2 is LOW. 2. must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period prior to the byte write enable inputs being sampled. 3. Full width WRITE can be initiated by , to are LOW. 4. ZZ is LOW.
Rev.0.4, Jun. 2002, page 18 of 22
;;; ;;
HM66WP18512, HM66WP36256
Read-Write Cycle
t CYC
;;; ;; ;;;; ; ; ;;; ; ;;; ; ;;; ;;; ;;;
t CH t CL
CLK
ADV/
t SA t HA
Address
A1
A2
A3
A4
t SW t HW
t SCE t HCE
*2
*3
t SD t HD
D
High-Z
D (A2)
D (A4)
D (A4+1)
D (A4+2)
t CA
t CLZ
t CHZ
Q
High-Z
*3
t CLZ
t CHZ
Q (A1)
Q (A3 )
High-Z
Single READ
Single WRITE
Single READ
BURST WRITE
H or L Undefined
Notes: 1. Q (A3) refers to output from address A3. 2. and CE2 have timing identical to . On this diagram, when is LOW, is LOW and CE2 is HIGH. When is HIGH, is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. does not cause Q to be driven until after the following clock rising edge. 4. ZZ is LOW.
Rev.0.4, Jun. 2002, page 19 of 22
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HM66WP18512, HM66WP36256
Power-down State
CLK tPDS tZZI tPUS ZZ ISUPPLY IISB2Z tRZZI ALL INPUTS (except ZZ) DESELECT or Read Only DESELECT or Read Only Outputs(Q) High-Z Power-down State with Data retention
;
DON' T CARE Notes: 1. The terms of tPDS and tPUS have to be that is LOW. 2. Data-output is not guaranteed during the cycle when transition of ZZ from low to high occurs.
Rev.0.4, Jun. 2002, page 20 of 22
HM66WP18512, HM66WP36256
Package Dimensions
HM66WP18512FP, HM66WP36256FP Series (FP-100H)
Preliminary
80 81
22.00 0.10 20.00 51 50
As of January, 2002
Unit: mm
16.00 0.10
14.00
100 1 *0.32 0.08 0.30 0.06 0.575 30
31
*0.17 0.05 0.15 0.04
1.60 Max
0.10 M
0.65
1.40
1.00 0.825
0 - 10
0.50 0.10
0.1
*Dimension including the plating thickness Base material dimension
0.10 0.05
Hitachi Code JEDEC JEITA Mass (reference value)
FP-100H Conforms -- 0.95 g
Rev.0.4, Jun. 2002, page 21 of 22
HM66WP18512, HM66WP36256
Disclaimer
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Sales Offices
Hitaci, Ltd.
Semiconductor Integrated Circuits Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: (03) 3270-2111 Fax: (03) 3270-5109
URL
http://www.hitachisemiconductor.com/
For urter inormation rite to
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive San Jose,CA 95134 Tel: <1 (408) 433-1990 Fax: <1(408) 433-0223 Hitachi Europe Ltd. Electronic Components Group Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44 (1628) 585000 Fax: <44 (1628) 585200 Hitachi Europe GmbH Electronic Components Group Dornacher Strae 3 D-85622 Feldkirchen Postfach 201, D-85619 Feldkirchen Germany Tel: <49 (89) 9 9180-0 Fax: <49 (89) 9 29 30 00 Hitachi Asia Ltd. Hitachi Tower 16 Collyer Quay 20-00 Singapore 049318 Tel : <65-6538-6533/6538-8577 Fax : <65-6538-6933/6538-3877 URL : http://semiconductor.hitachi.com.sg Hitachi Asia Ltd. (Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886-(2)-2718-3666 Fax : <886-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://www.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852-2735-9218 Fax : <852-2730-0281 URL : http://semiconductor.hitachi.com.hk
Copyright Hitachi, Ltd., 2002. All rights reserved. Printed in Japan.
Colophon 6.0
Rev.0.4, Jun. 2002, page 22 of 22

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